In this position you will be working within the Server Development Group (SDG), developing a ground breaking custom high performance SOC. This is an great opportunity to join the front-end design team as either in either a logic design and integration or Pre-Si verification role, early in the product lifecycle, as we enter the technology readiness (TR) phase, then move into design and execution (EXE). This program will include innovation in system to achieve performance across a broad scope of system components including computing (core/un-core), interconnect (on-die, on-MCP, off-MCP), silicon technologies, packaging, reliability and system software.
The responsibilities will be tailored to the candidate’s skills and expertise for either logic design and integration or pre-Si verification.
In the Logic Design role you will ensure the logic design meets the architectural specifications including:
contributing at multiple levels on the micro-architecture features and specification.
Implementing block/sub-system level logic design (RTL) using System Verilog.
Working with structural design engineers (physical design) on timing closure of critical structures.
SOC level logic integration.
You must be able to balance design trade-offs with modularity, scalability, DFX requirements, chassis compliance, power, area, and performance.
In the Pre-Si Verification role you will ensure the logical design satisfies the architectural specification including:
Creating and optimizing the validation environment, tools and methodologies
Developing or using checking software to compare model behavior against a specification
Generating focused and random test cases, analyzing coverage and debugging failure cases
Writing software to provide controllability and observability into the architectural model
Analyzing micro-architectural features to identify possible problem areas
Must have a BS or MS in Electrical Engineering, Computer Engineering, or Computer Science and 5+ years of experience in RTL/Logic design or Verification on ASIC’s or IP blocks or SOC's using System Verilog RTL coding.
Strong background in computer architecture
Strong analytical ability, problem solving and communication skills
Ability to work independently and at various levels of abstraction
Demonstrable experience writing System Verilog
Programming experience in C++, Perl and Assembly Algorithms and digital logic
Familiarity with a range of internal and 3rd-party logic design tools
Strong communication and team work stills.
The ideal candidate will be able to demonstrate the following behaviors:
Experience with SoC integration and/or verification.
Experience in DFX, design for test, debug, and manufacturing.
Experience in post-Si validation/debug
UVM/OVM testbench experience
Ability to work effectively with both internal and external teams/customers is expected.
Ability to mentor other engineers and technically guide them.
Capable of working in a high performing team to deliver the results required from the organization.
Facilitator of direct and open communication, diversity of opinion, and debate.
This is an Intel Federal Position
This position involves work on a U.S. Government contract which may impose certain security requirements. The government may require that you certify your citizenship status. If you are not a U.S. citizen, the government may require you to pass a security check before you can be approved to work on the project. Please note that any offer by Intel for this position is conditioned upon meeting and/or passing the U.S. Government's security check requirements should the government impose these requirements.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.