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Job ID: JR0043451
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Sr Logic Design Engineer

Job Description

Candidate will be responsible for all aspects of Logic design, u-arch definitions, validation test plan definition related to high speed SERDES PHY designs.

These PHY's are capable of 8/10/16/32Gbps data-rates, multiple protocols USB, PCIe, Display, mipi etc and with capability of deep low-power states.

The candidate is expected to define and design power-management schemes involving several power-domains and execute with quality checks through UPF, SPYGLASS tools.He will also be Providing IP integration support to SoC customers and represents RTL team.


Qualifications

Minimum Requirements:

  • Masters in Electrical/Computer Engineering with minimum 5 years of Logic design experience 
  • 5+ years of experience in logic design. High speed SERDES PHY related Logic design experience preferred
  • 3+ years of experience in multiple power-domain logic design and quality checks with UPF/SPYGLASS. 

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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