Candidate will be responsible for all aspects of Logic design, u-arch definitions, validation test plan definition related to high speed SERDES PHY designs.
These PHY's are capable of 8/10/16/32Gbps data-rates, multiple protocols USB, PCIe, Display, mipi etc and with capability of deep low-power states.
The candidate is expected to define and design power-management schemes involving several power-domains and execute with quality checks through UPF, SPYGLASS tools.He will also be Providing IP integration support to SoC customers and represents RTL team.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.