This position is for SoC Architect for Mobility/Converged mobility/client devices with broader expertise in clocking, power management, security, debug, IO plan, high speed IOs, real time subsystems, peripheral IOs. The successful candidate will be responsible for:- Converting product landing zone requirements into high level architectural specification-Should develop deep understanding of various IPs, NoCs, Memory organization etc., to able to do right trade-offs and come with a right Architecture specification. - Performing hardware and software partitioning- Working closely with design, validation and physical design teams in successfully converting architectural specification to implementation.-Should be able to influence and drive the design to make right design choices. - Responsible for RTL reviews, test plan reviews, problem debug on both pre-silicon and post-silicon enviroments, finding workarounds, physical/structured design reviews.- Working with firmware/software teams in ensuring product quality and features
- 12-20+ years of experience in SoC/ASIC/FPGA development with minimum 5 years of experience in three or more SoC microarchitecture/architecture areas such as clocking, power management, security, debug, IO plan, high speed IOs, real time subsystems, peripheral IOs, media subsystem, memory controller, display subsystem, imaging.- Experience in SoC development tools and flows including RTL coding.- Exposure to clocking, power management, security, debug, IO plan, boot flows, high speed IOs, DDR memory is highly desired.- Strong written and verbal communication skills. Ability to manage stakeholders across different geographies.- Excellent team playerInside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.