Creates bottoms up elements of chip design including but not limited to FET, cell, and block level custom layouts, FUB level floor plans, abstract view generation, RC extraction and schematic to layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, auto place and route algorithms, floor planning, full chip assembly, packaging, and verification.
Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments.
Requires expansive knowledge and practical application of methodologies and physical design.
BSEE or MSEEAt least 5-7 years of Layout experience in Advanced nodes 14 nm and 10nm
Have been exposed to Design Rules review and handled complex Layout blocks
Extensive use of Virtuoso IC12.3
Involved in Floorplanning, use of TPA and involved in discussions with Foundry on mitigating Design Rule changes.