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Job ID: JR0041431
Job Category: Intern/Student
Primary Location: Kulim, KDH MY
Other Locations: Malaysia, Penang;
Job Type: Intern

Physical Design Graduate Trainee

Job Description

Creates bottoms up elements of chip design including but not limited to FET, cell, and block level custom layouts, abstract view generation and schematic-to-layout verification and debug using phases of physical design development including customer polygon editing, floor planning and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.


Qualifications

Bachelor Degree in Electrical and Electronics Engineering. Strong technical knowledge in VLSI Design. Can work independently with minimum supervision.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.



Other Locations

Malaysia, Penang;

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