Your responsibilities will include but not be limited to:
- Block-level floor planning - Logic synthesis of design blocks
- Formal Equivalence Verification FEV - Auto Place-and-Route APR using Synopsys ICC tools - Timing verification using Synopsys PrimeTime as well as Intel tools - Physical verification - Layout vs. Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Manufacturability checks DFM - Analog signal specific requirements/checks- Assist in the preparation of the full-chip layout design database for introduction to manufacturing
Must have a BS/MS in Electrical Engineering, Computer Engineering, or Computer Science and 6+ years of experience in the following areas: - Synopsys SoC design tools, flows and methodology ICCDP, Design Compiler, IC Compiler/ICC, Primetime, VCS, Verilog - TCL, Perl, programming
Additional Preferred Qualifications:
-RTL/Logic design Verilog, VCS, etc. -Layout cleanup expertise DRCs, density, ipc, etc.
-Circuit design -Computer architecture
-Strong analytical ability, problem solving and communication skills
-Ability to work independently and at various levels of abstraction -Python, C and/or C++ programmingInside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.