Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
1 Candidate with 12+ years of experience in Timing-Closure/Timing Sign-off of highly complex SoC's. 2 Should have proven track record of successfully leading multiple Tape-Out's in Deep submicron technology. Preferably 16nm and beyond. Candidate must possess in depth expertise in the area of timing closure, timing sign-off, constrains generation using Industry standards tools such as Prime time . 3 Able to work with multiple IP partners and cross function teams to manage quality and timing integration aspects. 4 Candidate must have experience in hierarchical timing sign off of large SoC. 5 Good team player and ability to lead small team of senior technical members. 6 Good communication skills and ability to collaborate/partner with various teams across the organization.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.