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Job ID: JR0039647
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Package Substrate/PCB Layout Engineer

Job Description

We are looking an exceptional candidate to work in a challenging, fast paced environment developing next generation optical modules and engines so that we grow our market share and contribute to Silicon Photonics Product Division's mission to transform and lead datacenter connectivity and enable Intel's differentiation in the networking space. In this position, you will responsible for the design and development of advanced packaging substrate and printed circuit boards and/or subsystems for Intel Silicon Photonics products and sub-component verification. Your responsibilities will include but not be limited to: Performing layout and routing studies that lead to cost reduction, design solutions, improvements in manufacturability and reduced time to market TTM. Creating Ball map and interfacing with board layout engineer for ball map optimization. Placing and routing complex, high speed, multi-layer packaging substrate and circuit boards 1.Developing Layout BKMs 2.Creating documentation 3.Understanding of layout requirement for high speed signals and power distribution network 4.Understanding of mechanical requirements. Interfacing with design engineers, manufacturing engineers, signal integrity engineers, architect and/or technologists, purchasing personnel, onshore and offshore PKG/PCB manufactures and assembly houses for the successful packaging/board completion-Generating all outputs required for fabrication of packaging/board. Providing feedback on bump map and break-out study on bump area and interfacing with IC designers for bump map optimization. Providing feedback on board partitioning, and recommending design changes. Driving state of the art technologies into Intel packaging substrate/board development.-Pilot new tools and give feedback. Build and maintain library for general layout guidelines


MS with 3+ Years  of experience  in PKG/PCB layout, and competency in industrial CAD toolset for Package Substrate / Printed Circuit Boards PCB design such as Cadence

3+ years  of experience in electronics packaging in related environments, SiP, PoP, flipchip BGA, wafer level CSP, etc.

Experience with signal integrity, EMI* design issues, Cadence* or MentorGraphics* schematic capture tools, Cadence* Allegro Package Design APD* and Allegro* and Constraint Manager layout tools.

Knowledge in Electrical Circuits desirable-Knowledge of transmission line theory impedance control, skew, crosstalk etc. and high-speed Package Substrate/Printed Circuit Boards PCB design desirable

Good understanding of PCB manufacturing process

Highly desirable familiarity with HVM off-shore board fabrication houses and their technology limitations to comprehend during board design/layout

Good verbal and written communication skills are required, as is a highly disciplined approach to problem solving

Must be a self-starter capable of working with minimal supervision in a team

Knowledge of Windows* and UNIX* platforms, Perl would be an added advantage

Experience with Microsoft* Office* tool suite

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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