Job Description: Work as a part of the SOC integration team. Own both subsystem integration as well as global fabrics. Works closely with validation, physical and architecture teams creating the infrastructure as well as debugging and root causing design defects. Analyzes and uses results to drive bug fixes into both SOC RTL as well as subsystems.-Own subsystem integration work collaboratively with subsystem team to ensure correctness.-Own global fabrics integration work collaboratively with phys design team as well as architecture team to ensure architectural correctness of the implementation as well as satisfying physical requirements-Work in close collaboration with full chip validation team to assist in debug
Responsibilities and duties:
You will be responsible for the RTL integration of one or more IPs/subsystems into the server SoCs, starting with Tech Readiness through RTL1.0 and Tape-In. Techology Readiness TR work will include assessing new IPs/features, TFM proposed changes design effort/complexity, etc.
You will ensure that the incoming SIPs/HIPs you are responsible for meet the quality expectations for each SoC milestone and meet SoC design schedules.
You will work closely with the SoC Verification and Emulation teams to debug failures, with the SoC Structural Design team on timing constraints and exceptions, etc.
In addition, you will collaborate with the SIP/HIP teams, track IP bugs, scope and define netlist ECOs, identify bug workarounds, assess the impact of bugs and make recommendations on bug fixes.
You will also be responsible for milestone and paranoia checklist reviews and post-Silicon debug support.
Educational requirements for this position are a BSEE/CE minimum, MS preferred.
Also required are 5-10 years' experience in IC/SoC Design, integrating internal/3rd party IPs into SoC products.
Experience in all phases of logic development lifecycle from high-level specification to tape-out and production
Knowledge of DFX - Scan, JTAG, VISA, etc. Experience using 1 or more: Synopsys Coretools, VCS/Modelsim, Synopsys Design Compiler, Spyglass, Lint and one or more scripting languages
Experience using 1 or more of the following languages: Verilog, System Verilog, Perl, Tcl, Python C/C++.
Desired qualifications:Candidates should have design/ uArch experience DFX preferred
Knowledge/experience in Unified Power Format UPF methodology implementation and simulation and OVM/UVM are desirable
Candidates should also have experience with RTL simulators, VCS preferred
Good interpersonal skills and the ability to work in a highly cooperative team environment across several time zones are also desirable.
In this role you will be part for the Scalable Performance CPU Development Group SDG design team, working on next-generation Xeon server product SOCs and IPs.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.