In this position, you will be working alongside a World-class SoC System on a Chip design team within the Scalable Performance CPU Development Group SDG delivering next-generation Xeon products and related IPs for Server markets.
You will perform all aspects of the SoC design flow from high-level block design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. U
Your responsibilities will include but not be limited to:
- Block-level floor planning - Logic synthesis of design blocks - Formal Equivalence Verification FEV - Auto Place-and-Route APR using Synopsys ICC tools - Timing verification using Synopsys PrimeTime as well as Intel tools - Physical verification - Layout vs. Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Manufacturability checks DFM
- Assist in the preparation of the layout design database for introduction to manufacturing
Must have a BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science with 5+ years of industry experience.
Experience with CMOS transistor level circuit fundamentals, VLSI hardware design, and programming.
Additional Preferred Qualifications:
RTL/Logic design Verilog, VCS, etc.Electronic Design Automation tools, flows and methodology ICCDP, Design Compiler, IC Compiler/ICC, Primetime, VCS, Verilog Layout cleanup expertise DRCs, density, ipc, etc.
Circuit design Computer architecture TCL, Perl and/or C++ programming
Strong analytical ability, problem solving and communication skills
Ability to work independently and at various levels of abstraction.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.