Responsibilities will include:
Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
Participates in the development of Architecture and Microarchitecture specifications for the Logic components.
Provides IP integration support to SoC customers and represents RTL team. Collaborating with cross discipline stake holders in defining micro-architecture, implementing RTL in System Verilog and integrating other IPs into the design.
You will contribute to specifications at multiple levels, including the HAS and MAS micro-architecture spec.
You must be able to balance design trade-offs with modularity, scalability, DFX requirements, chassis compliance, power, area, and performance.
You will provide IP integration support to SOC customers and represent RTL and the IP team.
BS, MS, or PhD degree in Electrical Engineering with 3 to 8 years of relevant industry experience in digital VLSI design.
Experience in Logic design using System Verilog Micro-architecture trade-offs and documentation, Multiple clock domain design, IOSF Sideband and Chassis State machine design, TAP Controller and DFX Simulation.
Debug experience using VCS/Verdi Customer support and debug for SOCs Synthesis and Perl / C-shell Standard SOC Design tools and methodologies.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
California, Santa Clara;