The candidate will be part of the Silicon design team chartered with delivering IP and Subsystem designs to multiple server SOCs across Intel.
Candidate responsibilities include the following:
-Define and enhance methodologies for pre-silicon validation of high complexity IP/SoC designs improving the overall efficiency and velocity of the pre-silicon validation team.
-Interact closely with the architecture and design teams, influencing product definition, implementation and validation.
- Create, define and develop system validation environment and test suites.
-Responsible for the development of methodologies, execution of validation test plans, test sequences and directed tests.
The role requires the following attributes in the candidate:
Hands-on verification experience and proficiency using System Verilog and OVM/UVM2.
Proven track record in ASIC verification from environment development to tests development.
Experience in development and deployment of verification strategies and methodologies across teams and organizations.
Experience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage.
Experience with protocols such as IDI, IOSF and PCI-Express protocols
Candidate will have a Bachelor's degree in Electrical or Computer Engineering with 8+ years of experience of experience as a Pre-Silicon Validation designer OR a Master's degree in Electrical or Computer Engineering with 6+ years of experience as a Pre-Siilicon Validation designer.
Candidate will have knowledge in Digital/microprocessor Design, Computer Architecture, VLSI design, and Software/Programming .Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
California, Santa Clara;