In this position, you will be involved in validating IP I/O Interfaces at IP block and system level. Your responsibility includes create test plans for IP RTL Validation, develop functional test content and automation scripts to enable test to run across various environments/platforms eg simulation, FPGA, Emulation, Silicon in Pre and Post Silicon. Lastly analyzes and debugs failures encountered to ensure a high quality IP release.
- Good knowledge in system logic, computer architecture, PC's component and ecosystem. - Strong programming skills in C, C++, Python, Perl, Java and etc. - Some Hands-on experience using lab test equipment such as oscilloscopes, logic analyzers and software or kernel debug tools is a plus. - Highly independent with pro-activeness and self-initiatives. - Creativity in problem solving and logical thinking- Good understanding about Operating Systems and Device Drivers would be a plus.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.