You will be part of Intel Architecture Cores Group IACG group within PEG, in the Big Core IP development team driving Intel's latest CPU's in the World's leading process technologies. Your responsibilities will include but not limited to: Performing Static Timing Analysis STA. Finding solutions for extremely high frequency timing challenged design. Driving timing convergence for hierarchical design. Provide feedback and influence floorplanning. Working with logic designer, circuit designer , PnR owners for finding solutions of timing paths
You must possess a Masters Degree in Electrical or Computer Engineering with at least 3 or more years of experience in related field or a Bachelors Degree with at least 5 years of experience. Preferred Experience:Timing Analysis and convergence experience of extremely high speed designs. Circuit/cell level analysis of timing paths. Solid understanding of Circuit design and synthesis. STA experience on 10nm or below process nodes. STA experience on Processor designs is a plus. Excellent communication skillsInside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.