You will be part of Intel Architecture Cores Group IACG group within PEG, in the Big Core IP development team driving Intel's latest CPU's in the World's leading process technologies. Your responsibilities will include but not limited to: Layout design of Datapath and Register Files using semi-automated tools, flows, methodology along with manual polygon editsBlock level/sub-chip level floor-plan, Layout integration, power grid planning, clock routingAbstract view generation and full-chip assemblyRC extraction, RC aware routing both manual and semi-autoCoordination with circuit designerReliability Verification EM/SH/IR, etcPhysical verification DFM, DRC, LVS, Density, AntennaDevelop layout design methodologies
You must possess a Master's Degree in VLSI or Electronics or equivalent with at least 3 years of experience in related field or a Bachelor's Degree in E&C or Electrical Engineering or equivalent with at least 5 or more years of experience or Diploma in E&C with at least 6 years of experience.Preferred Experience: -Layout design of high speed Datapath or Register file or custom memory-Understanding of Layout design Convergence at Block/Section Level -Basic understanding of timing analysis is plus-Scripting knowledge is plus -Strong verbal and written communication skillsInside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.