You will be part of Intel Architecture Cores Group IACG Group within Platform Engineering Group, in the Big Core IP development team driving Intel's latest CPU's in the World's leading process technologies.Responsibilities will include but not limited to: 1. Driving Design Convergence of Datapath & Register File designs of Core blocks, characterization and quality checks to meet the design targets of high performance, and low-power digital design as per schedule 2. Develop design methodologies 3. Design Convergence at Block/Section Level 4. Coordination with Layout & Fub/Section Floor planning. 5. Low Power Solutions 6. Static timing analysis
Candidate must possess a Masters Degree in Electrical or Computer Engineering with at least 9 or more years of experience in related field or a Bachelors Degree with at least 11 years of experience.Preferred Experience: - Digital Design Experience, with experience in Custom digital and/or Register File design, and Section/Full-Chip level convergence, Timing Analysis, Floor planning - Familiarity with Verilog/VHDL - Strong verbal and written communication skills - Hands on Logic Design experience is a plus.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.