This particular role is focused on PCIe architecture and IO sub-system development.
Your responsibilities include but are not limited to:
Develops innovative solutions for new problems and/or develops innovative improvements to existing solutions.
Identifies, analyzes and resolves sub-system and/or SoC design and architecture weaknesses.
Determines, specifies and evaluates the viability of complex hardware features and structures, and ensures that software and hardware designs interface correctly.
Influences the shaping of future products by significantly contributing to the architecture used across design families.
Creates documentation to capture hardware architecture for the benefit of SoC design teams and supports these SoC design teams in their implementation efforts.
The ideal candidate should exhibit behavioral traits that indicate:
Strong problem solving and communications skills
Excellent written and verbal communications.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous school, industry jobs and/or research experience.
MS in electrical or computer engineering with 7+ years of experience.
Demonstrated experience in computer architecture in general, and I/O architectures such as PCIe specifically, ideally with knowledge of multiprocessor cache coherency.
Exposure to design, validation and performance analysis tools
8+ years of relevant industry experience
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.