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Job ID: JR0039044
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: Oregon, Hillsboro;
Job Type: Experienced Hire

Datacenter RAS Architect

Job Description

Come join our Datacenter Processor Architecture team! We drive the definition of Intel's datacenter and server microprocessors from first concept, through design, validation and manufacturing.

We work directly with Intel's largest customers to gain a deep understanding of real-world needs, applications and work closely with Intel business units, platform teams, front-end design and validation team while collaborating with Intel's fabs to help optimize power, performance and cost.

Our team is looking for a candidate to architect advanced RAS Reliability, Availability, Serviceability and Error Handling capabilities and solutions for datacenter microprocessor and SoCs.

Responsibilities:

  • Define, document and communicate RAS and Error Handling requirements to components/ subsystems, and review implementations for correctness and completeness.
  • Assess and identify error mitigations to address the needs of a wide range of market segments.
  • Participate in new product development, comprehend customer technical requirements, develop architectural solutions to meet those requirements
  • Author specifications and other technical collateral
  • Work with design and verification teams to ensure implementation is in accordance with the specification


Qualifications

Minimum Requirements:

  • Bachelor's + 6 years or a Master's +4 years or PhD + 2 year of relevant work experience in datacenter or server CPU architecture and logic design and validation. Focus area should include RAS architecture and interaction with operating system software and platform firmware in a datacenter.
     

Preferred Qualifications:

  • Knowledge of modern architectural techniques regarding reliability of microprocessors.
  • 6+ years of experience in architecture/logic design, including 3+ years of experience in processor RAS features, error handling, detection, and recovery
  • In-depth understanding of the interaction of machine check architecture and error flows with system firmware/software.
  • Detailed knowledge of multiprocessor system architecture, memory and input- output subsystems, high-speed interconnects, operating systems/hypervisors, platform firmware, Error correcting codes (ECC).
  • Experience in RTL development design environments
  • Experience successfully interacting with cross-disciplinary teams, tracking deliverables and milestones, with attention to detail.
  • Strong debug experience.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.



Other Locations

Oregon, Hillsboro;


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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