Performs logic design, Register Transfer Level RTL coding, and simulation to generate functional units, and subsystems for inclusion in SubSystem & full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team in various forums.Drive testplan/coverage etc from functional expertise point of view.Responsible for maintaining overall design quality matrices and associated design quality checks for achieving first time silicon ready IPs.
B.Tech./M.Tech from reputed institute IIT/NIT with Minimum 10-14 years experience in RTL/Logic design .Experience in high speed serial links like PCIe & knowledge of coherency concepts is desired.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.