The position is for SW/HW student in the Full Chip Timing Integration team which is a part of the CDG Design group. You will participate in the definition, development and execution of automatic solutions supporting all design needs in FC Timing domains.You will work closely with worldwide CPU design teams and SW development groups on development and execution of FC timing flows. You will be familiar with design environment, flows, tools, methodologies and optimization methods used at Intel.You can leave your impression on future FC timing methodologies.
Bsc. or MSc. student in Computer Science, Software or Hardware with software skills Engineering.Second semester & up, with at least 3 semesters left to graduation.Software background is a must Linux/Perl/Tcl/SQL are advantage.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.