Senior Design Engineer STA
- Working with Architecture and Design team to understand timing specification
- Define timing specification for project and subsystems
- Develop and validate timing constraints, debug constraints related issue, provide feedback to logic design team to improve timing performance
- Work with physical design and IP team for IP timing budget and provide feedback on timing closure
- Hierarchical timing closure and timing signoff
- Help improve timing signoff methodologies and infrastructure
Inside this Business Group
- Bachelors degree in EE with 10+ years of work experience or Masters degree in EE with 8+ years of work experience.
- Multiple tapeout experience in deep submicron, preferably experience in 14nm and below
- In depth knowledge and experience of Static timing analysis and timing signoff
- Hands on experience of timing closure at full chip and block level, SDC development and timing budgeting
- Experience in industry STA tools , primetime and primetime SI
- Experience in TCL/Perl/Python a plus
- Understanding of physical design PnR , synthesis is desired
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.