We are game changers, plain and simple. Step inside our world and you will find one brilliant mind after another - all working together in a spirit of collaboration that is simply contagious.
We are looking for you as Physical Design Engineer. In this position, you will be part of a highly-dynamic Digital Development team for Power Management ICs and RF Transceivers.
You will use your solid digital physical implementation know-how and state-of-the-art RTL to GDS methodologies, tools and flows to develop complex low power designs for our innovative communications platform products. You're going to work closely with the System Engineering, Circuit Design, RTL Design and analog Layout teams.
We offer a demanding position in an international company. You will work on challenging topics as a member of a cross-functional team of experts in a leading-edge technical environment. The position opens up the opportunity to gain a broad insight into leading-edge communications products and is ideally suited for applicants with a focus on a technical career.
What you’ll do:
Inside this Business Group
Qualifications: You should possess a University / University of applied sciences: master or bachelor degree in Electrical Engineering or Information Technology required. Work experience in physical design of at least 5 years is required We expect a highly-motivated technical expert with good communication and presentation skills. Strong interests in problem solving and an attitude to convince people of own ideas as well as openness towards novel technical directions are mandatory. The candidate should be capable of working in multi-disciplinary / site / cultural teams. The successful candidate should possess hands-on experience of industry standard RTL to GDSII development flow, methodologies and EDA tools, with a proven track record in delivering complete RTL to GDSII projects. Required technical skills are: Comprehensive knowledge to the complete digital P&R flow Experience in logic synthesis, constraints and STA/PTSI Experience in chip/block level floor planning and P&R Experience in CTS and timing closure Experience of power planning, power sign-off and IR Drop Analysis Experience in crosstalk noise analysis, physical verification, LVS and DRC Experience in DFT, MBIST, scan, coverage Experience with Synopsys EDA tools spanning the RTL to GDSII considered desirable but not essential What we offer you: We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth. Have a chance to participate in Intel Great Place to Work program which groups people who love running, cycling, squash, tennis, cross fit, photography, and many, many more. Chill out with unlimited amount of coffee, tea, and soft drinks. Charge internal batteries during energetic team events We offer a competitive salary and financial benefits such as bonuses, retirement plans, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards eligibility at the discretion of Intel Corporation. We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs and amenities, flexible work hours, time off, recreational activities, discounts on various products and services, and many more creative perks that make Intel a Great Place to Work! Creating and extending computing technology to connect and enrich the lives of every person on Earth- that's our vision, is it yours? We are changing the world at Intel.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.