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Job ID: JR0037194
Job Category: Engineering
Primary Location: Haifa, IL
Other Locations:
Job Type: Experienced Hire

Pre-Silicon Validation Engineer – CPV

Job Description
Ensures platform and its components have the best performance and power balance specifically focusing on graphics hardware components. Research and development of next generation platform designs to continually improve the performance. Conducts system analysis on proprietary and competition platforms, develops advanced hardware tuning and overclocking.


Qualifications

Job description:Pre-Silicon validation engineers are responsible to ensure the logic correctness during the development of each new Intel CPU product before it is being shipped to production. The role includes developing dedicated verification environments and tools, while driving a complex process of exercising the design to verify its logical correctness. These environments are developed using unique, state-of-the-art languages and tools, and advanced software engineering methodologies. Various validation techniques are used, such as simulation, emulation, formal verification, and digital/analog verification, while offering a unique Hardware-Software experience. In addition to various tools, languages and validation methodologies, engineers will develop expertise with Intel Architecture and Micro Architecture and will be deeply involved in the process of defining new Intel features. They are expected to be independent, creative, with the ability to innovate new solutions and demonstrate uncompromised quality during their work. There are open positions for Pre-Silicon validation engineers in [Haifa, Yakum, Jerusalem] Intel sites.Position is for both Experienced Pre-Silicon validation engineers. Skills:Engineers should possess a BSC or MSC degree in Electrical Engineering, Computer Engineering, Software Engineering or Computer Science. Additional qualifications include: - Knowledge in Very Large Scale Integration VLSI design and/or verification - Experience in developing validation collaterals in emulation environment would be an added advantage- Experience in developing Register Transfer Level RTL validation environment would be an added advantage- Experience in working with Verilog/SVTB* and/or OVM/UVM* and/or Emulation would be an added advantage- Familiarity with CPU architecture would be an added advantage

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