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Job ID: JR0036402
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations:
Job Type: Experienced Hire

STA timing Validation

Job Description


Qualifications

In this highly visible role, you will be at the center of a FPGA design effort on the latest Intel process technology and interfacing with all disciplines.

  • You will have a direct impact on getting functional FPGA products to our customers quickly.
  • You will be responsible for all aspects of timing closure spanning the entire project cycle from RTL design, synthesis, constraints development, helping physical implementation team with optimizing designs for timing, providing ECO guidance and driving the final timing sign-off for complex IPs and sub-systems.
  • You will have the unique opportunity to interact closely with our Software team (Quartus) and characterize timing models that represents IP timing behavior for Quartus tool and influence performance optimizations for the FPGA products.

The position requires thorough knowledge of the SOC design timing closure flow and methodology.

The ideal candidate will meet the following requisites:

  • At least 8+ years hands-on experience in ASIC timing constraints generation and timing closure
  • Expertise in Primetime and methodologies for timing closure with a good understanding of OCV, aging, noise and cross-talk effects on timing.
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced process technology nodes.
  • Must have a strong knowledge of timing corners/modes and process variations.
  • Should be comfortable in understanding of low-power techniques including clock gating, power gating and multi-voltage designs
  • Proficient in scripting languages Tcl, python and Perl
  • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different cross-functional groups.Self starter and highly motivated

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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