Candidate must possess a Masters Degree in Electrical or Computer Engineering with at least 7 or more years of experience in related field or a Bachelors Degree with at least 9 years of experience.
Should have exposure to leading technology nodes: 14nm, 10nm, 7nm.
Must have participated in all stages of the design. floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREMWell versed with the Static Timing Analysis, Timing Closure methodologies.
Should be able to provide clear directions to the team on Back End flows.
Well aware of place and route methodologies and hands on experience with timing convergence
Good communication skills to negotiate with stakeholders.
Work closely with Project Leader for creating schedule, tracking and raising issues / risks to project management.
Participate in Mentoring new joinees in the group on technical skills.
Provide inputs for CAD/DA team from Design Implementation perspective.
Work closely with DFT team on scan aspects and provide inputs from physical design.
Continuously work on methodology and productivity improvements.
Self-motivated, conflict resolution skills, and experience working with global teams across time zones Detail oriented and schedule driven.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.