Sr. DFT Engineer
Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
Inside this Business Group
Candidate should possess a Bachelors or Masters degree in Computer/ Electrical/Electronics Engineering with 4+ yr experience. Strong knowledge of DFT architecture, design, methodologies and tools - Scan, MBIST, Analog DFT, JTAG, etc. Hands on experience with minimum of 4+ years design/validation experience with strong/proven debug skills. A very good team player with good interpersonal, planning and communication skills
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.