• Develop binning and yield strategy to meet requirements of the newest FPGA products. This includes defining bin-splits, developing models to improve yield/binning predictability, establishing targets/limits to control yield, and the development/bring-up of binning circuits.
• Drive for yield optimization through process improvements in product performance and power. Engage worldwide teams on yield optimization across cross-functional areas such as manufacturing setup, test program, and wafer fabrication process targeting/tuning.
• Define and develop failure analysis / failure isolation (FA/FI) strategy for next generation FPGA products. This includes:
o Examining product architecture and manufacturing setup to understand requirements.
o Automation/tools development for efficient & accelerated electrical failure analysis (EFA).
o Participation in DFT/DFX (design for test/manufacturing) definition to improve product manufacturability.
• Drive for functional yield improvement through collaboration with test/validation content developers and circuit designers to isolate and root cause silicon failures caused by manufacturing defect.
• BS/MS in Electrical/Electronic Engineering or equivalent, with >5 years of industry experience in semiconductors design or manufacturing. • Proven experience in post-silicon debug/troubleshooting, including hands-on experience with multiple ATE tester platforms and test vectors. • Well-versed with scan/ATPG, memory BIST, fault isolation models and test algorithms. Strong digital logic knowledge. • Expert understanding of binning methodology and yield enhancement processes/methods, across wafer and package level testing. • Possess ability to perform basic statistical and data analysis, including correlation study with tools such as JMP. Good working experience with SQL/Perl/TCL/Python are advantages.