Power- and Timing-Optimized Generation of Hardware-Dependent Software Description
Today, in System-on-Chip SoC design an abstract single source description of the HW/FW interface is state of the art.
By means of a set of code generators the abstract interface description can be automatically translated in various realizations of the interface, e.g. register access functions for the Hardware Abstraction Layer HAL on FW side and the register RTL implementation on HW side. Thanks to the single source concept inconsistencies and errors can be avoided, which are the major drawback of the classical "handwritten paper spec" approach.
In this internship / master thesis the concept of a single source description / code generation shall be extended from the HAL layer to the low level FW driver layer. The low level FW driver typically takes a set of functional parameters as input and translates them into a set of bit fields organized in HW registers.
In addition to implementing a driver that just fulfills functional requirements, degrees of freedom in organizing bit fields can be exploited for an optimization with respect to power and timing or further criteria.
Summary of Tasks:
Inside this Business Group
• Strong interest in embedded SW/FW design and HW design methodology
• Good programming skills in C/C++-
• Ideally knowledge in SystemCQualification
• Master student of Computer Sciences, Information Electronics, Mechatronics
or similar JKU/FH/TU
Intel is one of the largest suppliers of chips for the communications market. The Intel Communications group is focused on designing and building communications technologies such as Ethernet connectivity products, optical components, communications processing solutions and broadband products.