Ethernet IP, enable chip-to-chip, board-to-board, or box-to-box connectivity in system designs. They satisfy the needs of a broad spectrum of applications and leverage the integrated transceivers in our FPGA and ASIC devices. You will be part of an engineering team that focuses on developing state-of-the-art Ethernet IPs. You will be working on advanced device architectures, design definition, implementation and verification. You will also be developing design examples, simulation models, accompanied by a rich set of technical documentation.
Inside this Business Group
Bachelors or Master's degree in EE, CE or CS, or equivalent.Familiarity or experience in RTL design with Verilog and/or VHDL is required.Familiarity or experience with RTL verification and timing analysis/closure on Linux/UNIX platforms is a strong plus.Familiarity with Perl, C++, Java and shell scripts is a plus.Strong skills in communication, initiative, promote innovation and teamwork.Highly motivated to learn and adapt to fast-changing technologies and environments.Demonstrates fundamental values such as accountability, integrity and a winning mindset