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Job ID: JR0025005
Job Category: Contract Employee
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Intel Contract Employee

Sr. CAD Manager, ASIC Flow Architect and Lead

Job Description

Job Description Summary

This is a contract opportunity that will last no longer than 2 years but has the opportunity to convert to a regular/indefinite opportunity at any time.

This Contract position is part of Intel's Centralized Design Acceleration and Operations team CDAO working on the development and support of next generation IC design flows for Analog Mixed-Signal, Digital, ASIC or full custom circuits. This position functions as a technical leadership role in the development of these design flows for multiple engineering customers Internal or External using industry standard EDA software such as Cadence, Mentor, Synopsys, etc

Responsibilities Include (but are not limited to)

  • Can be responsible for new EDA tool evaluations, selections, support, collateral creation PDK, FDK or CAD flow development focusing on the introduction of Next Generation technologies such as Silicon Photonics, Perceptual Computing or Intel Labs.
  • Implement creative solutions on the fly to accelerate IC design and silicon tapeout of non-volatile memory products and/or adjacent solutions critical to Intel's virtuous cycle of growth.


Qualifications

Required Skills and Experience (Must Have)
- Minimum of a Bachelor of Science degree in Electrical Engineering or Computer Engineering Computer Science with at least 10 years of experience in IC/ASIC Design or Computer Aided Design CAD, OR a Masters Degree in Electrical Engineering or Computer Engineering Computer Science with at least 7 years of experience in IC/ASIC Design or Computer Aided Design CAD.

- Solid track record with Cadence, Synopsys and/or Mentor tolos

- Demonstrated expertise with various Electronic Design Automation EDA software, flows and architecture

- Solid understanding of Integrated Circuit IC simulation tools and related methodologies

- Experience in front-to-back digital or analog flows RTL to GDS expert, or SPICE to GDS expert

- Demonstrated experience mentoring, coaching, and leading small groups of junior engineers working across Intel sites

Preferred Skills and Experience (Nice to Have)
- Excellent programming skills: Unix, Perl, Python, Skill, Tcl, C/C++ or other- Practical experience and solid track record with data management software

- Experience with DesignSync, Mercurial, Git/Gatekeeper, or other related

- Prior experience in CMOS Design, ASIC Design, VLSI and Device Physics

- Experience interfaceing with engineers, senior managers and stakeholders by providing schedule updates and roadmap plans

- Demonstrate experience with Cadence DFII environment such as Schematic Composer and/or Virtuoso Layout Editor

- Demonstrate experience with Synopsys Digital tools such as Design Compiler DC, IC Compiler ICC, ICC2, Primetime PT and other Logic Design Automation tools or scripts

- Thorough understanding of RTL Synthesis, APR, Timing Closure Physical Design and Verification

- Demonstrated experience with Mentor Graphics software such as Calibre for DRC/LVS or Star-RCXT for Parasitic Extraction -

- Prior experience with Semiconductor startup company

- Familiarity with external Foundries

Inside this Business Group

Non-Volatile Solutions Memory Group:  The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices.  The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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