Description:In this position, candidate will be responsible to lead part of Physical Sign-Off Team and resolve any precess/flow related issues. This includes, drive the team to resolve issues in Physical Verification, Tape-In, DRC, LVS, ESD issues.Candidate will also be involved to interact with Full Chip Layout FCL team on physical domain issues.Candidate will also be involved with Full Chip Layout FCL team on Custom routing and Bump Map related issues.Candidate will also be responsible to drive the methodology development in Physical Verification Domain.In addition, be self-motivated with the initiative to seek constant improvements in the physical design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
Inside this Business Group
You must possess a Bachelor of Engineering degree or Maser of Engineering in Electrical and/or Electronics Engineering with 10+ relevant experience with the skills in logic design, synthesis, APR flows. Additional qualifications include: Good understanding of physical layout, manufacturabilityExperience with UNIX, Perl and TCL also desired in order to implement usable, flexible C-shell/ Perl/ TCL programs that automate tool/flow methodologies.oMust have hands-on experience with industry tools in one or more of these areas. Familiarity with Design Compiler, ICC and timing convergence tools would be added plus
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.