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Job ID: JR0023297
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations: California, Santa Clara;
Job Type: College Grad

Physical Design Engineer

Job Description

Candidate will be working as part of a team supporting RTL synthesis and place & route experiments using internal and external vendor tools to improve Intel's product Power, Performance, and Area, for existing and future process nodes on internal IA and external ARM/Imagination IP's. The team works in close collaboration with our partners in the process technology and design teams spanning CPU, Graphics, Imaging, Modem, and Servers. The primary focus of the team is to accurately predict the impact of process changes on density scaling and power/performance metrics thereby facilitating quick data-based decisions for scaling and power/performance commits going from one tech node to the next. The candidate for this position will be specifically expected to deal with changes to floorplan, corresponding scaling and its impact to power/performance, debug scaling/timing issues for the present tech node and predict how it would impact scaling/timing/power for the next tech node, improve cell utilization and transistor density metrics and keep pushing the power/performance envelope through critical path analysis, metal layer usage by the tool etc.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship.
 
Minimum Qualifications:

-Candidate must have a Master's Degree of Science in Electrical or Computer Engineering or any related discipline.

6 months to 1 year experience in:

- C/C++, Perl, TCL, Shell scripting.
- Placement and routing CAD tools

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth



Other Locations

California, Santa Clara;


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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