Responsibilities include owning Synthesis and APR activities of blocks in advance technology nodes. Need familiarity of all back end sign-off activities like STA, LEC, CLP, EM/IR, Layout Verification etc. Exposure to advanced clocking schemes and low power design techniques is a plus. Should have the ability to technically lead a team of engineer to own execution deliverable for the team.
Inside this Business Group
B.Tech/M.Tech with 8+ years of experience in VLSI physical design activities.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.