Inside this Business Group
Candidate should possess a Bachelor or Master of Science degree in Computer / Electrical / Electronics Engineering with more than 5 years of experience. As a SoC Design Engineer, you will be responsible for RTL integration at SoC, RTL quality checks and releasesHaving in-depth domain knowledge in one or more of the following areas is desired: CPU sub-system, ARM based / Atom Based, Graphics, Media, Display, High speed peripherals, IO peripherals, DDR/Dunit, On Chip buses like, OCP, AMBA, IoSFComplete understanding of SoC Design flows - from micro-architecture to structural design Hands on experience in RTL implementation, IP integration, RTL releases meeting the quality checks, which includes, Linting, CDC, synthesizability, constraints.Having experience in power aware design, UPF & multi-power domain checks will be of added advantage.Need to work with: 1 silicon architects to comprehend the design/RTL 2 verification engineers to meet the functional requirements & verify/ debug the design 3 structural design engineers to meet their requirements 4 Internal/External IP vendors 5 DFX & Debug teamsShould be strong in Digital design basics, experience in System Verilog coding, user of standard ASIC EDA tools like VCS, Lint, CDC, DC, Spyglass, LEC, Fishtail, etc., and expert user in one or more toolsExpected to have very good scripting skills, Unix user expertise, Bug filing systems, etc.,A very good team player with interpersonal and communication skills.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.