• Define validation methodology and plans for post-silicon validation of timing models, FPGA core logic and routing fabric circuits.
• Develop FPGA validation pattern sets. Drive capability on various tester platforms to enable volume characterization.
• Holistically drive to achieve correlation between simulation models and actual performance on silicon to meet product quality goals. This includes:
o Collaboration with worldwide cross-functional teams: Engage with chip designers and software model engineers to define validation requirements and analyze silicon results.
o Performing statistical analysis to deep dive into data trends.
o Examining product architecture and silicon material composition.
• Participate in binning definition and strategy from product performance perspective.
• As part of a highly technical team, you will have the opportunity to innovate on and establish new validation methodology, as well as new volume characterization process improvements.
• BS/MS in Electrical/Electronic Engineering or equivalent, with >8 years of industry experience in semiconductors design or manufacturing. • Strong statistical analysis and digital logic knowledge. • Exposure to multiple ATE tester platforms and proficiency in automation scripting are advantages.