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Job ID: JR0017598
Job Category: Engineering
Primary Location: Penang, PNG MY
Other Locations:
Job Type:

IP Logic Design Engineer

Job Description
  • High-speed serial interface IP with transceivers (e.g. CPRI, RapidIO)
  • Architecture and Design (Based on latest specifications, RTL design)
  • Verification (e.g. verification IP/methodologies/framework, bus functional models, regression tests)
  • New product release or rollout support
  • Customer technical support
  • Device support and features

• BSEE/MSEE/PhD, with 5-8 years of digital design experience. • Familiarity or experience in RTL design with Verilog and/or VHDL is required. • Familiarity or experience with RTL verification and timing analysis/closure on Linux/UNIX platforms is a strong plus. • Knowledge of high speed serial system interfaces (such as Ethernet, IEEE 1588, CPRI or Serial Rapid IO) is a strong plus. • Familiarity with Perl, C++, Java and shell scripts is a plus.

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