Apply Now    
Job ID: JR0017404
Job Category: Engineering
Primary Location: Singapore, Central Singapore SG
Other Locations:
Job Type:

Staff Engineer SoC Design

Job Description
  • IP integration: Able to follow IP integration guidelines, both physical and functional and perform SoC integration.
  • Floor planning: Be involved with chip-level floorplan considering IP and package constraints
  • Integration checks: Perform all necessary IP and subsystem integration checks
  • Clock and reset distribution: Plan and develop the clock and reset distribution strategy
  • DFT insertion: Be involved with the DFT insertion process
  • ASIC sign-off: Be involved with all aspects of the ASIC sign-off procedure.



Qualifications
• Master/Bachelor’s Degree in Electronics Engineering or equivalent • 12+ years of experience in SoC/Block Design. • Integrate complex IPs into the SOC. • Work closely with other engineers that are members of the SOC Design, SOC Design Verification, Emulation , DfT and Physical Design teams • Fluent in RTL languages (e.g. VHDL, Verilog) and excellent digital design skills. • Most familiar and hands on experience with Front End design methodologies and tools (Design, STA, Synthesis, Verification , CDC) • Knowledge about deep-submicron SoC low-power chip design aspects such as power-gating, clock-gating, clock tree • Understanding of moderns Processor Subsystem Architectures is required, e.g. MIPS, ARM ,x86. • Domain Knowledge on standard interfaces and bus protocols is advantageous, e.g. PCI/USB/PCI-E /ETHERNET/SPI/I2C/AXI/AMBA • Domain knowledge of XDSL, Ethernet L2/3, wireless LAN is preferred • English (fluent in spoken and written) • Team player who integrates well into a multi-national team

Apply Now    

What would you like to do now?

Connect with Us

Get Job Alerts

Get started
Student Center

Find out more about working at Intel

Learn more
Education

Jobs@Intel Blog

Learn more

Grow your network of opportunities