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Job ID: JR0007012
Job Category: Engineering
Primary Location: Munich, DE
Other Locations:
Job Type: Intel Contract Employee

Mixed Signal Design Engineer - time limited contra

Job Description

We are developing the key leading edge high speed Physical Layer Interfaces MIPI-DPHY, MPHY, as well as different Interface IP subsystems for Intel products.

We offer you to be part of a development team that ambitiously contribute to shaping and driving the future of the next mobile communication solutions.

We are looking for an experienced digital design verification engineer with a strong technical background in design, simulation and verification of advanced digital.

High Speed Interface circuits in deep-submicron CMOS technologies.

You will be part of the PHY/Subsystem development team.

Your responsibilities will include but not be limited to:

  • RTL development in a DF2 environment, RTL coding using VHDL, verilog & systemverilog
  • Custom Analog Circuit design
  • Mixed signal IF circuit specification and architecture definition
  • Analog / mixed signal modelling - Concept definition, circuit schematic capture and simulation
  • Pre and Post-Layout Verification of the analog circuits and the IP top-level
  • Providing input to R2G flow, sdc and reviewing output timing files, supervision of MS/Analog layout
  • Support lab evaluation and debugging of test chip and product samples
  • Support of product testing and products teams


• University of applied sciences: degree in Electrical Engineering, Applied Physics or Information Technology
• Work experience at least 5 years or equivalent
• Experience in industry standard design software /EDA tools for analog design entry, simulation, layout and physical verification Spectre, ADMS, Cadence frame work
• Experience in complex analog/mixed signal design, modeling and co-verification and architecture
• Running mixed-signal verification using VCS/XA & AMS
• Designer to verify functionality with analog blocks
• Experience in high speed I/O Receiver, Transmitter, DLL, Clock Recovery, Jitter analysis, and Equalization schemes and CMOS High Speed interfaces Serdes, M-Phi, PCIe, at least in 28nm, with devices already in production, M-PHY competence would be a preference
• Solid experience in 28nm CMOS required, experience in 14nm or FinFet technology desired
• PLL circuit design desired
• Fluent English, German is desired

The candidate will work in a multicultural, multisite environment and beside of mastering the mentioned technical skills, he must have evident project team spirit, engagement, communication skills and clear orientation to results

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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