Develops preSilicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.
Inside this Business Group
Qualification: BE/BTech with 5 yrs experience or ME/MS/MTech with 3 yrs experienceExperience in pre-silicon designGood communication skills and a team playerExperienced in various aspects of DFT -SCAN insertion, ATPG & JTAG, BSCAN, MBIST. Job Description:RTL development and integration into Subsystems/System on ChipAutomation of DFT fabric generation using tools like xweave/jsonFamiliarity with key RTL tools/infrastructure like Lintra/Febe/FEV/VerdiHands-on debug on issues reported at various stage of development - IP/Chassis/Sub-systems/SoC.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.