• 15+ years of relevant experience. Degree in Electrical or Computer Engineering, graduate level or compensating experience. • Fluent in System Verilog and UVM methodologies. • Sound working experience with Port Arbitration ASIC and SerDes PHY • Working knowledge of PCIe 2.0 & AMBA protocols. • Experience in verifying DDR3/DDR4 interfaces. • Prior Working experience with VIP portfolio IP. • Scripting experience in PERL, Python, and Shell required, C/C++ preferred. • Expert level knowledge of EDA Functional simulators - Incisive/VCS. • Prior experience with Error Injection based verification preferred. • Demonstrated technical abilities and capable of leading and solving technical challenges. Ability to work cross-functionally. • Energetic. Self-driven. Good communication, organization, analytical, people, project planning, and leadership skills. • Proven success in development of complex custom ASIC products in advanced process nodes.