Staff Engineer Design For Test
Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
• 5+ years of DfT experience.
• Experience in Design for Test (DFT) of large, lower geometry SOC designs.
• Experience in DFT concepts, test mode.
• Good knowledge in Boundary Scan, ATPG Scan, and memory testing.
• Proficiency in VHDL/Verilog coding, test bench setup, test case creation and verification
• Proficiency in mixed signal IP verification such PCIe Phy, PLL etc
• Experience with industry standard tools for DFT and Verification (Synopsys, Cadence)
• Proficiency high level programming and scripting languages such as “C”, “C++”, Perl
• Knowledge or Experience in Test development and Product engineering will be an added advantage