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Job ID: JR0010839
Job Category: Engineering Management
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Hardware Design Manager

Job Description


Qualifications

Job Description:
Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost. Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides guidance on employee development, performance, and productivity issues. Plans and schedules daily tasks, uses judgement on a variety of problems requiring deviation from standard practices. Inadequacies and erroneous decisions would cause moderate inconvenience and expense.
Qualifications:
Responsible for leading a ASIC program and team of ASIC design and verification engineers. Major responsibilities include providing technical leadership, project schedules and tracking, and managing external vendor relationships. Responsibilities include:

• Participate in the design process starting with high-level conceptual and architectural discussions and ending with micro architecture and design partition within the ASIC.
• Implement blocks using Verilog and work with Verification Engineers to design the verification environment.
• Synthesize designs and make sure there are no design rules violations using available lint tools.
• Work with backend teams to address layout and timing issues and to optimize the area of the circuit.
• May be responsible for recruiting, coaching, and/or developing organizational talent.
• May be responsible for providing direction and/or guidance to exempt specialists and/or supervisory staff who exercise significant latitude and independence in their assignments. May supervise non-exempt employees.
• May be responsible for interfacing with external ASIC vendors and overseeing all associated aspects of backend development including, but not limited to:
o Floorplanning
o Physical Design
o DFT
o STA
o Power integrity

Requirements:
• BS or MS degree in Electrical Engineering
• 10+ years of front-end ASIC experience
• Prior experience managing and leading small teams
• Prior experience managing relationship with ASIC vendor
• Familiarity with all back-end disciplines: Physical design, DFT, STA, Power analysis, Packaging

Inside this Business Group

Deep Learning Solutions, Intel/Nervana are currently developing the Nervana Engine, an application specific integrated circuit (ASIC) that is custom-designed and optimized for deep learning.
You will be a key part of a silicon design team chartered with creating silicon IP and ASICs targeted at state of the art Deep Learning and Machine Learning algorithms.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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