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Job ID: JR0009859
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Pre-Silicon Validation Engineer

Job Description
Creates emulation/Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation/FPGA synthesis, partitioning and routing tools. Defines and documents RTL changes required for emulation/FPGA. Develops hardware and software collaterals and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation ease-of-use and improvement of equipment utilization.


Qualifications

Job Description: The successful candidate will be part of silicon design team chartered with delivering IP and ASICs targeted at state of the art Deep Learning and Machine Learning algorithms.

Responsibilities include the following:

Define and enhance methodologies for pre-silicon validation of high complexity IP/SoC designs improving the overall efficiency and velocity of the pre-silicon validation team. Interact closely with the architecture and design teams, influencing product definition, implementation and validation. Create, define and develop system validation environment and test suites. Responsible for the development of methodologies, execution of validation test plans, test sequences and directed tests.

Qualifications

Minimum Requirements: Education: BS in Electrical or Computer Engineering and 5+years of experience-a minimum of three years of experience developing verifications collateral in Verilog, System Verilog and UVM-SOC microarchitecture and system level skills-Experience with Perl, Python, Unix scripting

Inside this Business Group

Deep Learning Solutions, Intel/Nervana are currently developing the Nervana Engine, an application specific integrated circuit (ASIC) that is custom-designed and optimized for deep learning.
You will be a key part of a silicon design team chartered with creating silicon IP and ASICs targeted at state of the art Deep Learning and Machine Learning algorithms.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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