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Job ID: JR0009549
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Design Verification Lead

Job Description
Conducts or participates in multidisciplinary research in the design, development, testing and utilization of information processing hardware and/or electrical components, mechanisms, materials, and/or circuitry, processes, packaging, and cabinetry for central processing units (CPUs) and/or peripheral equipment. Prepares specifications, evaluates vendors, and analyzes test reports. Ensures products conform to standards and specifications. Develops plans and cost estimates and assesses projects to analyze risk. Develops procedures, analysis and design for computer components, products, and systems. Initiates, guides, and coordinates overall design and development of new ideas and products. Responds to customer/client requests or events as they occur. Develops solutions to problems utilizing formal education and judgement.


Qualifications

Design Verification Lead
Job Description

Responsible for defining and developing verification methodology, major verification components, testbench development, reference model, regression suite. Own components including stimulus generators, monitors and checkers scoreboards. Responsible for test planning, directed/constrained random test generation, debug failures, coverage collection, analysis and closure, Work closely with the design team to review specifications and architecture, define verification & coverage plans. Develop testbench, test content, reference model, and regression suite. Enable RTL and gate level functional verification, debug failures, manage bug tracking, and analyze and close coverage. Work with Architecture and RTL groups to provide solutions for complex technical challenges

Qualifications

Seeking an experienced Design Verification lead:-MS degree or PhD in Electrical Engineering or Computer Science with 10+ years of experience-Advance knowledge on ASIC verification flows including RTL design simulation, testbench architecture and testbench development-Knowledge of Networking architecture, network protocols and standards 10+ years of proven hands-on verification experience, experience and expertise on UVM, standard verification methodology UVM.-Coding experience within Verilog and/or System Verilog. Programming experience in C/C++ or similar language. Experience in Functional coverage, testplan development, System Verilog Assertions a plus-Experience writing scripts in Perl or Python-Excellent communication skills, team player, mentoring junior team members-Experience with continuous integration systems-Experience with verification using FPGAs and/or emulation platforms a plus

Inside this Business Group

Intel/Nervana DL Hardware - Nervana Engine delivers deep learning at ludicrous speed! Intel- Nervana is currently developing the Nervana Engine, an application specific integrated circuit (ASIC) that is custom-designed and optimized for deep learning.
You will be a key part of a silicon design team chartered with creating silicon IP and ASICs targeted at state of the art Deep Learning and machine learning algorithms.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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