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Job ID: JR0001242
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Debug Validation and Enablement Engineer

Job Description

Debug validation and enablement Engineer for Xeon Phi CPU who will develop and execute pre and post silicon functional validation plans for DFD features.Creates, defines and develops system validation environment and test suites for DFD features (e.g. CrashDump, VISA, StateDump). Uses and applies emulation and platform level tools and techniques to ensure performance to spec. Responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Presilicon Validation teams in improving postsilicon test content and providing feedback for future on die debug features.Leads DFD and tools integration and enabling in the lab, develops debug methodologies and guidance for validation and debug engineers. The debug enabling lead will own the release planning for the team and all relevant communication with stakeholders and partners.


Qualifications

Relevant knowledge in Pre/Post Si system validationBasic SW development skills. Familiar with PreSi solutions and its usages for HW/SW/FW validation Familiarity with debug tools LTB/ITP and NPK.Scripting using Python SV

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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