Be the first to develop, design and test wireline I/O circuits in Intel’s leading-edge technology node. Design PHY circuits covering wireline standards in serial, memory, and legacy high-voltage I/Os and integrate them into Intel’s first technology test chips. Use your design and measurement results to guide the next generation of process technology based on requirements for critical wireline interfaces. Work closely with process and product/IP engineers to anticipate interface requirements and use design and test results to accelerate process technology and product development.
Required skills: - Masters or Ph.D. degree in relevant field. - Excellent analog/mixed-signal design skills including specification, design and validation. - Experience designing and testing analog, clocking and/or wireline I/O blocks. - Ability to analyze and guide layout. - Familiarity with mixed signal design validation.