Creates Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation/FPGA synthesis, partitioning and routing tools. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve FPGA model usability for preSilicon and postSilicon functional validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the FPGA platform. Develops and applies automation aids, flows and scripts in support of FPGA ease of use and improvement of equipment utilization.
Inside this Business Group
You must possess a Bachelor's, Master's or a Ph.D. in Computer Engineering, Computer Science or Electrical/Electronics Engineering and preferably with experience in software development and strong interests in PC architecture.Strong FPGA design skills including familiarity with Xilinx & Altera tool flows with Verilog & VHDL. Knowledge/experience in x86 CPU architecture, computer system or CPU features, C/C++/assembly/Perl/Python programming or silicon validation/debug is an added advantage.