Develops pre-Silicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Executing Volume Regression Testing. Candidate should have good problem-solving, communication, and interpersonal skills.Specific responsibilities/duties Key Responsibilities: • Responsible for verification of design, architecture, golden models and micro-architecture using advanced verification methodologies • Responsible for understanding the design and implementation, defining the verification scope, developing/maintaining the verification infrastructure (Transactors, Testbenches, BFMs, Checkers, Monitors). • Definition and development of testplans, Functional coverage points, Assertions, Random/Directed tests to validate design. • Development of test bench components for a simulation and emulation-based environment: bus functional models, trackers, checkers, scoreboards, and testbench. • Running RTL simulations, developing testcases to execute the feature testplans debugging design/TB issues • Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes • Work with Software, tools, micro-architecture and full chip teams to ensure seamless validation.
Inside this Business Group
Minimum experience and skills: Candidate should possess a degree in Electrical Engineering, Computer Science or related field 2+ years of relevant experience. A Master’s degree is preferred. Candidate should have 2+ years of experience with the following:• Solid experience with HVL’s like SystemVerilog, or Specman • Familiarity with OOP’s concepts and OVM/UVM methodologies, C, C++ • Hands on experience with coding and developing testbench components like BFM’s, Monitors and Checkers/Scoreboards. • Good understanding of overall Validation flows tools • Familiarity with Functional Coverage, Code Coverage Assertions concepts methodologies Preferred experience and skills:• Knowledge Cache based designs, Cache Coherency flows, Power Management Flows is a big plus • Experience with Perl, Shell scripting, Makefiles, TCL a plus
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.